[MAGEEC] Chip variations: tests, results, and graphs

Alex J Lennon ajlennon at dynamicdevices.co.uk
Sun Jul 27 17:32:02 BST 2014


On 27/07/2014 17:27, James Pallister wrote:
> No JTAG - the chips are flashed with a bootloader, which is only
> active on chip reset. Everything is programmed via a USB-to-serial thingy.
>

Sorry, I don't think I'm understanding fully James. So the flash area
tests are via JTAG? I guess that would mean that the test is a read only
test?

(I'm just asking because I'm quite interested in power utilisation
during write/erase cycles vs read. If you're not doing that could I
suggest it might be an interesting test?)

BR. Alex

> On 27/07/14 17:25, Steve Kerrison wrote:
>>
>> Is JTAG connected during test runs? Interested to know how much
>> difference that makes, although it should be constant thus irrelevant.
>>
>> On 27 Jul 2014 17:13, "James Pallister"
>> <James.Pallister at bristol.ac.uk
>> <mailto:James.Pallister at bristol.ac.uk>> wrote:
>>
>>     Hi All,
>>
>>     Some preliminary findings on variations in the ATMEGA328 chips.
>>
>>     I've tested 28 chips. For each chip 9 tests were ran:
>>
>>     flash0
>>     	Test the area of flash 0x0800-0x0810
>>     flash1
>>     	Test the area of flash 0x080C-0x081C
>>     flash2
>>     	Test the area of flash 0x08FC-0x090C
>>     flash3
>>     	Test the area of flash 0x0FFC-0x100C
>>     ram0
>>     	Repeatedly access 0x0000 - 0x0020
>>     ram1
>>     	Repeatedly access 0xF007 - 0xF017
>>     alu
>>     	Perform combinations of mul, fmul, inc and dec
>>     nop
>>     	Lots of nops
>>     branch
>>     	Repeatedly branch randomly in low flash
>>
>>
>>     Each test was run 8 times, and outliers excluded. All were run in
>>     the same harness, with the same crystal, resistors, etc.
>>
>>     Results across each test. These show the distributions of the
>>     measurements taken, where the distribution consists of the 28 chips.
>>
>>
>>     From the first graph: there is a significant different, even on a
>>     day to day basis. I'm not sure what causes this - I'd expect the
>>     power to be lower at lower temperatures, which we don't see.
>>
>>     For each chip:
>>
>>     Mean power for each chip:
>>
>>
>>
>>     The average power changes quite a lot, going from < 80mW to >
>>     100mW. In almost all cases, the average power was higher on
>>     Saturday - not sure why this is, the temperature difference was
>>     only 3-4 degrees (and I'd expect the temperature to go down with
>>     lower temperature).
>>
>>     The chips tend to vary as a whole, e.g. rather than the ALU
>>     varying significantly in one part rather than another. The
>>     following graph marks the average power for each test, divided by
>>     test type (different color/marker combinations) per chip. This
>>     should allow hopefully allow us to do a calibration run first.
>>
>>     Legend for the above graph:
>>     Blue cross
>>     	ram1
>>     Red star
>>     	ram0
>>     Green plus
>>     	alu
>>     Black plus
>>     	flash3
>>     Green cross
>>     	flash2
>>     Blue star
>>     	flash1
>>     Red plus
>>     	flash0
>>     Black star
>>     	nop
>>
>>
>>
>>     Any thoughts / ideas for more tests are welcome.
>>
>>
>>     James
>>
>
>
>
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