--- Log opened Fri Aug 02 00:00:44 2013 | ||
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AWhetter | jeremybennett: What is the name of the boards that you were testing the benchmarks on? And is it a MIPS architecture? | 09:48 |
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@jeremybennett | I was testing on an 8-bit Atmel AVR architecture, specifically, the ATMega128 (same family as the Arduino uses). | 10:03 |
@jeremybennett | I was using a cycle accurate model generated by Verilator, but there should be no reason why you can't do the same on an Arduino, modifying as necessary for the ATMega328 | 10:04 |
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munaafghumran | simoncook: Kerstin has asked me to provide you some data so you can start 'populating' the ML<>compiler interface, she cc'd you in the email. Is what she suggested fine? So I can provide all the .c files, and would it be easier to have the feature vector in a seperate file, or together with the source code in one file? | 10:32 |
@jeremybennett | munaafghumran: simoncook is out for a couple of days, so you probably won't get a quick IRC reply. Probably best to send him email. | 10:33 |
@jeremybennett | BTW - did you see the Nigel Topham email. | 10:33 |
munaafghumran | ah, okay - thank you jeremybennett | 10:33 |
@jeremybennett | I expect Albert will be slower to reply - the French are usually on vacation through August. | 10:33 |
munaafghumran | yeah I did, he's forwarded it on to Mike O Boyle and Bjoern Franke who are both on vacation until mid august | 10:34 |
munaafghumran | I shall see if Albert sends an email through in the meanwhile | 10:34 |
AWhetter | Are we using MAGEEC as a noun to refer to the compiler itself? ie could I say "We are checking the correctness of the programs produced by the MAGEEC."? | 10:36 |
AWhetter | I'm starting to talk about memory allocation and when it is and isn't zeroed in my blog post. Is this too low level and detailed do you think? | 10:48 |
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@jeremybennett | MAGEEC is the project IMHO, not the product. The compilers are gcc and llvm. What simoncook is writing is a machine learning plugin. It needs a name. Ideas via the mailing list? | 12:09 |
amylaar_ | Wasteful Amperage Negating DSO. | 12:16 |
amylaar_ | If we need more than one plugin, we might be looking at a Set of Power Efficiency Loadable Libraries. | 12:29 |
amylaar_ | Hmm, there''s also a singular version, but a bit pretentious: Superior Power Efficiency Loadable Library. | 12:32 |
amylaar_ | Cybernetic Power Efficiency Learning Library | 12:36 |
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amylaar_ | The CPELL gcc plugin would also need to access some database regarding the relative merits of various options and parameters - can we call that "Trove of (Historical) Archived Utility of Machine Automated Translation Relative to GCC Invocation parameters" ? | 14:07 |
amylaar_ | Trove of (Historical) Archived Utility of Machine Automated Translation Relative to Used GCC Invocation parameters | 14:08 |
amylaar_ | OOps. | 14:08 |
amylaar_ | Trove of (Historical) Archived Utility of Machine Automated Translation Using Recorded GCC Invocation parameters | 14:11 |
jamespallister | Thats quite an esoteric word? | 14:11 |
amylaar_ | Trove of (Historical) Archived Utility of Machine Automated Translation Using Recorded GCC Invocations | 14:11 |
jamespallister | Thaumaturgy | 14:11 |
AWhetter | or THAUMATUG for short | 14:12 |
amylaar_ | Thaumarurgi is distilled Mageec. | 14:12 |
amylaar_ | s/Thaumarurgi/Thaumaturgi/ | 14:13 |
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@jeremybennett | AWhetter: Will you merge your changes into the low-power mainline when they are polished? | 15:32 |
AWhetter | jeremybennett: Yes. I'll add the ChangeLog entry once I merge it as well. | 15:34 |
AWhetter | Is there anything specific that you think needs polishing? | 15:34 |
@jeremybennett | No - I haven't looked at your code, just listened to the discussion. Might be worth you checking it can build with the AVR GCC compiler (just build standard GCC for target avr) | 15:42 |
jamespallister | jeremybennett: on the topic of AVR GCC, did you see that someone was asking about shift-optimizations for AVR on the GCC mailing list? | 15:44 |
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amylaar_ | I saw it, but I thought there is little point replying. | 16:04 |
amylaar_ | a) The correctness stuff is not done yet, neither libcstdc++ | 16:05 |
amylaar_ | b) I doubt the suggestions make much sense, considering the size constraints. | 16:05 |
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amylaar_ | Considering you bring this up here... is there a specific power angle to this? | 16:06 |
jamespallister | Not especially | 16:07 |
jamespallister | although efficiency is always good for energy | 16:07 |
amylaar_ | FWIW, if you use a post-reload split pattern, the stuff should stay split. | 16:07 |
amylaar_ | I guess he was talking about splitting the shifts in an expander, which would be subject to combine re-combining stuff. | 16:08 |
amylaar_ | I once wanted to have low-level shift instructions for the SH too. Didn't work to well with the register allocator. | 16:09 |
amylaar_ | After reload, you can split. | 16:09 |
jamespallister | I've been meaning to ask: -fschedule-insns and -fschedule-insns2: is the only difference between them the point the compilation when they schedule the instructions? | 16:11 |
amylaar_ | yes. | 16:11 |
amylaar_ | the former is before register allocation, the latter after it. | 16:11 |
jamespallister | Can you think of any reason why scheduling after register allocation would result in lower overall energy consumption? | 16:12 |
jamespallister | Sorry, the other way around | 16:13 |
jamespallister | The result we had was -fschedule instructions reduced energy significantly more than execution time, where as -fschedule-insns2 reduced time significantly more than energy | 16:13 |
amylaar_ | the latter can be plausibly explained: | 16:14 |
amylaar_ | mis-scheduled instructions cause stalls, which cost time, not necessarily as much power as parts of the chip sleep. | 16:15 |
amylaar_ | and after register allocation, we have a pretty good cost model for latencies, so it is to be expected that we can do effective scheduling, resulting mostly in time savings. | 16:15 |
amylaar_ | scheduling before register allocation is a bit hit-and-miss. | 16:16 |
amylaar_ | because we don't know the exact insn alternatives used, and also don't know yet about reload instructions inserted. | 16:17 |
amylaar_ | Do you have an instruction count / size correlation as well? | 16:17 |
jamespallister | Not easily available at the moment | 16:18 |
amylaar_ | What pre-reload scheduling is most useful for is scheduling high-latency operations that need extra registers available. | 16:18 |
jamespallister | Ah I see | 16:18 |
jamespallister | Is that potentially useful with SIMD units, like the NEON? | 16:19 |
amylaar_ | But I don't see how that would explain your observations. | 16:19 |
amylaar_ | What would make sense if sched1 was reducing register pressure in cases where there's sufficient slack in the schedule, and thus you save reload instructions, which cost not only time, but also get the memory interface active. | 16:20 |
amylaar_ | This was not historically the case in GCC, but maybe that's changed. Vladimir Makarov is both the scheduler and new register allocator maintainer, and ISTR a statement that i386 should be scheduled for reducing register pressure. | 16:22 |
jamespallister | OK, sounds like I may have to dig out some specific cases where enabling that option causes a reduction in energy | 16:23 |
AWhetter | jeremybennett: Just to let you know that I have written the first draft of my blog post and I'm just waiting on some feedback from Simon before sending it to the mailing list for a final check. I was hoping to have it finished by the end of today but I think it's more likely to be the end of the weekend now | 16:53 |
@jeremybennett | OK - no problem. I'm on vacation for two weeks, so send it direct to Andrew Back. | 17:46 |
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--- Log closed Sat Aug 03 00:00:50 2013 |
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